
`include "Comp.v"
`include "Controle.v"


module Decode (

	input				clock,
	input				reset,
	input				fw_if_id_stall,

	// Fetch.
	input		[31:0]	if_id_instrucao,
	input		[31:0]	if_id_proximopc,
	output	reg			id_if_selfontepc,
	output		[31:0]	id_if_rega,
	output	reg	[31:0]	id_if_pcimd2ext,
	output	reg	[31:0]	id_if_pcindex,
	output	reg	[1:0]	id_if_seltipopc,

	// Execute.
	output	reg			id_ex_selalushift,
	output	reg			id_ex_selimregb,
	output	reg			id_ex_selsarega,
	output	reg	[2:0]	id_ex_aluop,
	output	reg			id_ex_unsig,
	output	reg	[1:0]	id_ex_shiftop,
	output	reg	[4:0]	id_ex_shiftamt,
	output		[31:0]	id_ex_rega,
	output	reg	[2:0]	id_ex_msm,
	output	reg	[2:0]	id_ex_msl,
	output	reg			id_ex_readmem,
	output	reg			id_ex_writemem,
	output	reg			id_ex_mshw,
	output	reg			id_ex_lshw,
	output		[31:0]	id_ex_regb,
	output	reg	[31:0]	id_ex_imedext,
	output	reg	[31:0]	id_ex_proximopc,
	output	reg	[2:0]	id_ex_selwsource,
	output	reg	[4:0]	id_ex_regdest,
	output	reg			id_ex_writereg,
	output	reg			id_ex_writeov,

	// Forwarding.
	output		[4:0]	id_fw_regdest,
	output				id_fw_load,
	output		[4:0]	id_fw_addra,
	output		[4:0]	id_fw_addrb,
	output		[31:0]	id_fw_rega,
	output		[31:0]	id_fw_regb,
	input		[31:0]	fw_id_rega,
	input		[31:0]	fw_id_regb,

	// Registradores.
	output		[4:0]	id_reg_addra,
	output		[4:0]	id_reg_addrb,
	input		[31:0]	reg_id_dataa,
	input		[31:0]	reg_id_datab,
	output				id_reg_ena,
	output				id_reg_enb

	);

	...

endmodule



